Patent Literature 1 (see FIG. 34) discloses an arrangement in which NAND elements are supplied with (i) respective outputs from respective stages of a shift register included in a gate driver and (ii) a DCG signal, and in which the NAND elements supply their respective outputs to respective scanning signal lines. This arrangement makes it possible to (i) simultaneously select all scanning signal lines by causing the DCG signal to be active when a liquid crystal display device is turned on and off, and thus (ii) write a Vcom (common electrode potential) to all pixels.